Optical phase locked loop for transparent inter-satellite communications
نویسندگان
چکیده
منابع مشابه
High Speed Delay-Locked Loop for Multiple Clock Phase Generation
In this paper, a high speed delay-locked loop (DLL) architecture ispresented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which canbe triggered by double edges of the input signals. In addition, the blind zone is removed due to the elimination of reset signal. Theref...
متن کاملInter-Satellite Communications for Small Satellite Systems
Small satellite technology has opened a new era in aerospace engineering by decreasing space mission costs, without greatly reducing the performance. The concept of formation flying using small satellites is becoming popular because of their potential to perform coordinated measurements of remote sensing space missions. The current state of art in satellite communications is a one hop link betw...
متن کاملhigh speed delay-locked loop for multiple clock phase generation
in this paper, a high speed delay-locked loop (dll) architecture ispresented which can be employed in high frequency applications. in order to design the new architecture, a new mixed structure is presented for phase detector (pd) and charge pump (cp) which canbe triggered by double edges of the input signals. in addition, the blind zone is removed due to the elimination of reset signal. theref...
متن کاملPhase Locked Loop Circuits
1. Definition. A PLL is a feedback system that includes a VCO, phase detector, and low pass filter within its loop. Its purpose is to force the VCO to replicate and track the frequency and phase at the input when in lock. The PLL is a control system allowing one oscillator to track with another. It is possible to have a phase offset between input and output, but when locked, the frequencies mus...
متن کاملDual Phase Detector Based Delay Locked Loop for High Speed Applications
In this paper a new architecture for delay locked loops will be presented. One of problems in phase-frequency detectors (PFD) is static phase offset or reset path delay. The proposed structure decreases the jitter resulted from PFD by switching two PFDs. In this new architecture, a conventional PFD is used before locking of DLL to decrease the amount of phase difference between input and outpu...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Optics Express
سال: 2005
ISSN: 1094-4087
DOI: 10.1364/opex.13.003816